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?2005 silicon storage technology, inc. s71264-01-000 1/05 1 the sst logo and superflash are registered trademarks of silicon storage technology, inc. these specifications are subject to change without notice. advance information features: ? single 2.7-3.6v read and write operations serial interface architecture ? spi compatible: mode 0 and mode 3 33 mhz max clock frequency superior reliability ? endurance: 100,000 cycles (typical) ? greater than 100 years data retention low power consumption: ? active read current: 7 ma (typical) ? standby current: 8 a (typical) flexible erase capability ? uniform 4 kbyte sectors ? uniform 32 kbyte overlay blocks fast erase and byte-program: ? chip-erase time: 70 ms (typical) ? sector- or block-erase time: 18 ms (typical) ? byte-program time: 14 s (typical) auto address increment (aai) programming ? decrease total chip programming time over byte-program operations end-of-write detection ? software status hold pin (hold#) ? suspends a serial sequence to the memory without deselecting the device write protection (wp#) ? enables/disables the lock-down function of the status register software write protection ? write protection through block-protection bits in status register temperature range ? commercial: 0c to +70c ? industrial: -40c to +85c ? extended: -20c to +85c packages available ? 8-lead soic 150 mil body width ? 8-contact wson (5mm x 6mm) all non-pb (lead-free) devices are rohs compliant product description sst?s serial flash family features a four-wire, spi-compati- ble interface that allows fo r a low pin-count package occu- pying less board space and ultimately lowering total system costs. sst25vf512a spi serial flash memory is manufac- tured with sst?s proprietary, high-performance cmos superflash technology. the split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared wi th alternate approaches. the sst25vf512a device significantly improves perfor- mance, while lowering power consumption. the total energy consumed is a function of the applied voltage, cur- rent, and time of application. since for any given voltage range, the superflash technology uses less current to pro- gram and has a shorter erase time, the total energy con- sumed during any erase or program operation is less than alternative flash memory technologies. the sst25vf512a device operates with a single 2.7-3.6v power supply. the sst25vf512a device is offered in both 8-lead soic and 8-contact wson packages. see figure 1 for the pin assignments. 512 kbit spi serial flash sst25vf512a sst25vf512a512kb serial peripheral interface (spi) flash memory
2 advance information 512 kbit spi serial flash sst25vf512a ?2005 silicon storage technology, inc. s71264-01-000 1/05 1264 b1.0 i/o buffers and data latches superflash memory x - decoder control logic address buffers and latches ce# y - decoder sck si so wp# hold# serial interface f unctional b lock d iagram
advance information 512 kbit spi serial flash sst25vf512a 3 ?2005 silicon storage technology, inc. s71264-01-000 1/05 pin description figure 1: p in a ssignments table 1: p in d escription symbol pin name functions sck serial clock to provide the timing of the serial interface. commands, addresses, or input data are latched on the rising edge of the clock input, while output data is shifted out on the fa lling edge of the clock input. si serial data input to transfer commands, addresses, or data serially into the device. inputs are latched on the rising edge of the serial clock. so serial data output to transfer data serially out of the device. data is shifted out on the falling edge of the serial clock. ce# chip enable the device is enabled by a high to low transition on ce#. ce# must remain low for the duration of any command sequence. wp# write protect the write protect (wp#) pin is used to enable/disable bpl bit in the status register. hold# hold to temporarily stop serial communication wi th spi flash memory without resetting the device. v dd power supply to provide power supply (2.7-3.6v). v ss ground t1.0 1264 1 2 3 4 8 7 6 5 ce# so w p# v ss v dd hold # sck si top view 1264 08-soic p1.0 8- lead soic 8- contact wson 1 2 3 4 8 7 6 5 ce# so w p# v ss top view v dd hold # sck si 1264 08-wson p2.0
4 advance information 512 kbit spi serial flash sst25vf512a ?2005 silicon storage technology, inc. s71264-01-000 1/05 product identification memory organization the sst25vf512a superflash memory array is orga- nized in 4 kbyte sectors with 32 kbyte overlay blocks. device operation the sst25vf512a is accessed through the spi (serial peripheral interface) bus compatible protocol. the spi bus consist of four control lines; chip enable (ce#) is used to select the device, and data is accessed through the serial data input (si), serial data output (so), and serial clock (sck). the sst25vf512a supports both mode 0 (0,0) and mode 3 (1,1) of spi bus operations. the difference between the two modes, as shown in figure 2, is the state of the sck signal when the bus master is in stand-by mode and no data is being transferred. the sck signal is low for mode 0 and sck signal is high for mode 3. for both modes, the serial data in (si) is sampled at the rising edge of the sck clock signal and the serial data output (so) is driven after the falling edge of the sck clock signal. figure 2: spi p rotocol table 2: p roduct i dentification address data manufacturer?s id 00000h bfh device id sst25vf512a 00001h 48h t2.0 1264 1264 f02.0 mode 3 s ck si so c e# mode 3 don't care bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mode 0 mode 0 high impedance msb msb
advance information 512 kbit spi serial flash sst25vf512a 5 ?2005 silicon storage technology, inc. s71264-01-000 1/05 hold operation hold# pin is used to pause a serial sequence underway with the spi flash memory without resetting the clocking sequence. to activate the hold# mode, ce# must be in active low state. the hold# mode begins when the sck active low state coincides with the falling edge of the hold# signal. the hold mode ends when the hold# signal?s rising edge coincides wi th the sck active low state. if the falling edge of the hold# signal does not coincide with the sck active low state, then the device enters hold mode when the sck next reaches the active low state. similarly, if the rising edge of the hold# signal does not coincide with the sck active low state, then the device exits in hold mode when the sck next reaches the active low state. see figure 3 for hold condition waveform. once the device enters hold mode, so will be in high- impedance state while si and sck can be v il or v ih . if ce# is driven active high during a hold condition, it resets the internal logic of the device. as long as hold# signal is low, the memory remains in the hold condition. to resume communication with the device, hold# must be driven active high, and ce# must be driven active low. see figure 18 for hold timing. figure 3: h old c ondition w aveform write protection the sst25vf512a provides software write protection. the write protect pin (wp#) enables or disables the lock- down function of the status register. the block-protection bits (bp1, bp0, and bpl) in the status register provide write protection to the memory array and the status regis- ter. see table 5 for block-protection description. write protect pin (wp#) the write protect (wp#) pin enables the lock-down func- tion of the bpl bit (bit 7) in the status register. when wp# is driven low, the execution of the write-status-register (wrsr) instruction is determined by the value of the bpl bit (see table 3). when wp# is high, the lock-down func- tion of the bpl bit is disabled. active hold active hold active 1264 f03.0 sck h old# table 3: c onditions to execute w rite -s tatus - r egister (wrsr) i nstruction wp# bpl execute wrsr instruction l 1 not allowed l0allowed hxallowed t3.0 1264
6 advance information 512 kbit spi serial flash sst25vf512a ?2005 silicon storage technology, inc. s71264-01-000 1/05 status register the software status register provides status on whether the flash memory array is available for any read or write oper- ation, whether the device is write enabled, and the state of the memory write protection. during an internal erase or program operation, the status register may be read only to determine the completion of an operation in progress. table 4 describes the function of each bit in the software status register. busy the busy bit determines whether there is an internal erase or program operation in progress. a ?1? for the busy bit indi- cates the device is busy with an operation in progress. a ?0? indicates the device is ready for the next valid operation. write enable latch (wel) the write-enable-latch bit indicates the status of the inter- nal memory write enable latch. if the write-enable-latch bit is set to ?1?, it indicates the device is write enabled. if the bit is set to ?0? (reset), it indicates the device is not write enabled and does not accept any memory write (program/ erase) commands. the write-enable-latch bit is automati- cally reset under the following conditions: power-up write-disable (wrdi) instruction completion byte-program instruction completion auto address increment (aai) programming reached its highest memory address sector-erase instruction completion block-erase instruction completion chip-erase instruction completion table 4: s oftware s tatus r egister bit name function default at power-up read/write 0 busy 1 = internal write operation is in progress 0 = no internal write operation is in progress 0r 1 wel 1 = device is memory write enabled 0 = device is not memory write enabled 0r 2 bp0 indicate current level of bloc k write protection (see table 5) 1 r/w 3 bp1 indicate current level of bloc k write protection (see table 5) 1 r/w 4:5 res reserved for future use 0 n/a 6 aai auto address increment programming status 1 = aai programming mode 0 = byte-program mode 0r 7 bpl 1 = bp1, bp0 are read-only bits 0 = bp1, bp0 are read/writable 0r/w t4.0 1264
advance information 512 kbit spi serial flash sst25vf512a 7 ?2005 silicon storage technology, inc. s71264-01-000 1/05 block protection (bp1, bp0) the block-protection (bp1, bp0) bits define the size of the memory area, as defined in table 5, to be software pro- tected against any memory write (program or erase) operations. the write-status-register (wrsr) instruction is used to program the bp1 and bp0 bits as long as wp# is high or the block-protect-lock (bpl) bit is 0. chip-erase can only be executed if block-protection bits are both 0. after power-up, bp1 and bp0 are set to 1. block protection lock-down (bpl) wp# pin driven low (v il ), enables the block-protection- lock-down (bpl) bit. when bpl is set to 1, it prevents any further alteration of the bpl, bp1, and bp0 bits. when the wp# pin is driven high (v ih ), the bpl bit has no effect and its value is ?don?t care?. after power-up, the bpl bit is reset to 0. auto address increment (aai) the auto address increment programming-status bit pro- vides status on whether the device is in aai programming mode or byte-program mode. the default at power up is byte-program mode. table 5: s oftware s tatus r egister b lock p rotection 1 protection level status register bit protected memory area bp1 bp0 000none 1 (1/4 memory array) 0 1 0c000h-0ffffh 2 (1/2 memory array) 1 0 08000h-0ffffh 3 (full memory array) 1 1 00000h-0ffffh t5.0 1264 1. default at power-up for bp1 and bp0 is ?11?.
8 advance information 512 kbit spi serial flash sst25vf512a ?2005 silicon storage technology, inc. s71264-01-000 1/05 instructions instructions are used to read, write (erase and program), and configure the sst25vf512a. the instruction bus cycles are 8 bits each for commands (op code), data, and addresses. prior to executing any byte-program, auto address increment (aai) programming, sector-erase, block-erase, or chip-erase instructions, the write-enable (wren) instruction must be executed first. the complete list of the instructions is provided in table 6. all instructions are synchronized off a high to low transition of ce#. inputs will be accepted on the rising edge of sck starting with the most significant bit. ce# must be driven low before an instruction is entered and must be driven high after the last bit of the instruction has been shifted in (except for read, read-id and read-status-register instructions). any low to high transition on ce#, before receiving the last bit of an instruction bus cycle, will terminate the instruction in progress and return the device to the standby mode. instruction commands (op code), addresses, and data are all input from the most significant bit (msb) first. table 6: d evice o peration i nstructions 1 1. a ms = most significant address a ms = a 15 for sst25vf512a address bits above the most signi ficant bit of each density can be v il or v ih bus cycle 2 2. one bus cycle is eight clock periods. 123 456 cycle type/operation 3,4 3. operation: s in = serial in, s out = serial out 4. x = dummy input cycles (v il or v ih ); - = non-applicable cycles (cycles are not necessary) s in s out s in s out s in s out s in s out s in s out s in s out read (20 mhz) 03h hi-z a 23 -a 16 hi-z a 15 -a 8 hi-z a 7 -a 0 hi-z x d out high-speed-read (33 mhz) 0bh hi-z a 23 -a 16 hi-z a 15 -a 8 hi-z a 7 -a 0 hi-z x x x d out sector-erase 5,6 5. sector addresses: use a ms -a 12 , remaining addresses can be v il or v ih 6. prior to any byte-program, aai-program, sector-erase, block-erase, or chip-erase operation, the write-enable (wren) instructi on must be executed. 20h hi-z a 23 -a 16 hi-z a 15 -a 8 hi-z a 7 -a 0 hi-z - - block-erase 5,7 7. block addresses for: use a ms -a 15 , remaining addresses can be v il or v ih 52h or d8h hi-z a 23 -a 16 hi-z a 15 -a 8 hi-z a 7 -a 0 hi-z - - chip-erase 6 60h or c7h hi-z- --- - --- byte-program 6 02h hi-z a 23 -a 16 hi-z a 15 -a 8 hi-z a 7 -a 0 hi-z d in hi-z d in hi-z auto address increment (aai) program 6,8 8. to continue programming to the next sequential address location, enter the 8-bit command, afh, followed by the data to be programmed. afh hi-z a 23 -a 16 hi-z a 15 -a 8 hi-z a 7 -a 0 hi-z d in hi-z d in hi-z read-status-register (rdsr) 05h hi-z x d out -note 9 9. the read-status-register is continuous with ongoing clock cycles until terminated by a low to high transition on ce#. -note 9 -note 9 note 9 enable-write-status-register (ewsr) 10 10. the enable-write-status-register (ewsr) instruction and the write-status-register (wrsr) instruction must work in conjunctio n of each other. the wrsr instruction must be executed immediately (v ery next bus cycle) after the ewsr instruction to make both instructions effective. 50h hi-z - - - - - - - - write-status-register (wrsr) 10 01h hi-z data hi-z - - -. - - - write-enable (wren) 06h hi-z - - - - - - - - write-disable (wrdi) 04h hi-z - - - - - - - - read-id 90h or abh hi-z 00h hi-z 00h hi-z id addr 11 11. manufacturer?s id is read with a 0 =0, and device id is read with a 0 =1. all other address bits are 00h. the manufacturer?s and device id output stream is continuous until term inated by a low to high transition on ce# hi-z x d out 12 12. device id = 48h for sst25vf512a xd out 12 t6.0 1264
advance information 512 kbit spi serial flash sst25vf512a 9 ?2005 silicon storage technology, inc. s71264-01-000 1/05 read (20 mhz) the read instruction outputs the data starting from the specified address location. the data output stream is con- tinuous through all addresses until terminated by a low to high transition on ce#. the internal address pointer will automatically increment until the highest memory address is reached. once the highest memory address is reached, the address pointer will auto matically increment to the beginning (wrap-around) of the address space, i.e. for 4 mbit density, once the data from address location 7ffffh had been read, the next output will be from address location 00000h. the read instruction is initiate d by executing an 8-bit com- mand, 03h, followed by address bits [a 23 -a 0 ]. ce# must remain active low for the duration of the read cycle. see figure 4 for the read sequence. figure 4: r ead s equence 1264 f04.0 c e# so si s ck add. 012345678 add. add. 03 high impedance 15 16 23 24 31 32 39 40 70 47 48 55 56 63 64 n+2 n+3 n+4 n n+1 d out msb msb msb mode 0 mode 3 d out d out d out d out
10 advance information 512 kbit spi serial flash sst25vf512a ?2005 silicon storage technology, inc. s71264-01-000 1/05 high-speed-read (33 mhz) the high-speed-read instruction supporting up to 33 mhz is initiated by executing an 8-bit command, 0bh, followed by address bits [a 23 -a 0 ] and a dummy byte. ce# must remain active low for the duration of the high-speed-read cycle. see figure 5 for the high-speed-read sequence. following a dummy byte (8 clocks input dummy cycle), the high-speed-read instruction outputs the data starting from the specified address location. the data output stream is continuous through all addresses until terminated by a low to high transition on ce#. the internal address pointer will automatically increment until the highest memory address is reached. once the highest memory address is reached, the address pointer will auto matically increment to the beginning (wrap-around) of the address space, i.e. for 4 mbit density, once the data from address location 07ffffh has been read, the ne xt output will be from address location 000000h. figure 5: h igh -s peed -r ead s equence 1264 f05.0 c e# so si s ck add. 012345678 add. add. 0b high impedance 15 16 23 24 31 32 39 40 47 48 55 56 63 64 n+2 n+3 n+4 n n+1 x msb msb msb mode 0 mode 3 d out d out d out d out 80 71 72 d out note: x = dummy byte: 8 clocks input dummy cycle (v il or v ih )
advance information 512 kbit spi serial flash sst25vf512a 11 ?2005 silicon storage technology, inc. s71264-01-000 1/05 byte-program the byte-program instruction programs the bits in the selected byte to the desired data. the selected byte must be in the erased state (ffh) when initiating a program operation. a byte-program instruction applied to a pro- tected memory area will be ignored. prior to any write operation, the write-enable (wren) instruction must be executed. ce# must remain active low for the duration of the byte-program instruction. the byte- program instruction is initiated by executing an 8-bit com- mand, 02h, followed by address bits [a 23 -a 0 ]. following the address, the data is input in order from msb (bit 7) to lsb (bit 0). ce# must be driven high before the instruction is executed. the user may poll the busy bit in the software status register or wait t bp for the completion of the internal self-timed byte-program operation. see figure 6 for the byte-program sequence. figure 6: b yte -p rogram s equence 1264 f06.0 c e# so si s ck add. 012345678 add. add. d in 02 high impedance 15 16 23 24 31 32 39 mode 0 mode 3 msb msb msb lsb
12 adva nce in fo rm at ion 512 kb it spi serial flash sst25vf512a ? 2 00 5 s i l i c on st or ag e te chno l o g y , in c. s7 12 64- 0 1 - 0 0 0 1 / 05 aut o ad dres s in cre m ent ( a ai ) pro g ram t h e a a i pr o g r a m in st r u ct io n a l l o ws m u ltiple b y tes of data to be pr og r a mmed wit hout re -issuing th e ne xt se quent ial ad dress location . this f e a t ur e d e cr eases to tal prog r a m- ming t i me whe n t he ent ire memo r y ar r a y is t o be pro- g r amme d. an aai pr og r a m instr u ction point ing to a pr ot ect ed memor y area will be ign o red . the selecte d ad dress r ange m u st be in the er ased st ate (ffh) when in i- t i ating an aai prog r a m instr u ction . pr ior t o an y wr it e oper ation , th e wr it e-enab le (wren) instr u ctio n m u st be e x e c ut ed. th e aai pro g r a m instr u ct io n is in itiat ed b y e x ecuting an 8- bit command , afh, f o llo w e d b y addr ess b i t s [a 23 -a 0 ] . f o llo wing t he addr esses , t he dat a is input se quen tially fro m msb ( b it 7) t o lsb (b it 0) . ce# m u st b e dr iv en high bef ore the aai prog r a m inst r u ction is e x ecute d . the user m u st po ll th e b u sy bit in th e soft w a r e sta t us reg i st er or w a it t bp f o r t he complet i on of ea ch int e r - na l self -t im ed byt e -pro g r am cycle . once t he de vice com - ple t es pr og r a mming b y te , th e ne xt sequen tial a ddre s s ma y be prog r a m , ent er t he 8 - bit comma nd, afh, f o llo w ed b y th e da ta t o be pro g r a mmed. whe n the last de sire d b y te ha d be en pr og r a mmed, e x ecu t e t he wr it e-disab le (wrdi ) instr u ctio n, 04h, t o ter m in ate aai. af ter e x ecut io n of th e wrdi com m and, t he user m u st poll t he st at us registe r t o en sur e th e de vice complet e s pr og r a mming . see figur e 7 f o r aai p r og r a mming seque nce . the r e is no wr ap mo de du r i ng aai pro g r a mming; once th e hig hest un prot ected memor y a ddre s s is r eached, th e de vice will e x it aai oper atio n and reset the wr ite-e n ab le- la tch b i t (wel = 0 ) . figure 7 : a uto a d dres s i nc reme nt (aai) p r o gram s equenc e c e# si s ck a[23:16] a[15:8] a[7:0] af data byte 1 af data byte 2 c e# si so s ck wr ite disab le (wrdi) instr uction to ter minate aai oper ation read status register (rdsr) instr uction to v e r ify end of aai oper ation 04 last data byte af 05 d out mode 3 mode 0 t bp t bp t bp 1264 f07.0 0 1 2 3 4 5 6 7 8 3 23 33 43 53 63 73 83 9 15 16 23 24 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 01 01234567 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5
advance information 512 kbit spi serial flash sst25vf512a 13 ?2005 silicon storage technology, inc. s71264-01-000 1/05 sector-erase the sector-erase instruction clears all bits in the selected 4 kbyte sector to ffh. a sector-erase instruction applied to a protected memory area will be ignored. prior to any write operation, the write-enable (wren) instruction must be executed. ce# must remain active low for the duration of the any command sequence. the sector-erase instruction is initiated by executing an 8-bit command, 20h, followed by address bits [a 23 -a 0 ]. address bits [a ms -a 12 ] (a ms = most significant address) are used to determine the sector address (sa x ), remaining address bits can be v il or v ih. ce# must be driven high before the instruction is exe- cuted. the user may poll the busy bit in the software status register or wait t se for the completion of the internal self- timed sector-erase cycle. see figure 8 for the sector- erase sequence. figure 8: s ector -e rase s equence block-erase the block-erase instruction clears all bits in the selected 32 kbyte block to ffh. a block-erase instruction applied to a protected memory area will be i gnored. prior to any write operation, the write-enable (wren) instruction must be executed. ce# must remain active low for the duration of any command sequence. the block-erase instruction is initiated by executing an 8-bit command, 52h or d8h, fol- lowed by address bits [a 23 -a 0 ]. address bits [a ms -a 15 ] (a ms = most significant address) are used to determine block address (ba x ), remaining address bits can be v il or v ih . ce# must be driven high before the instruction is exe- cuted. the user may poll the busy bit in the software status register or wait t be for the completion of the internal self- timed block-erase cycle. see figure 9 for the block-erase sequence. figure 9: b lock -e rase s equence c e# so si s ck add. 012345678 add. add. 20 high impedance 15 16 23 24 31 mode 0 mode 3 1264 f08 .0 msb msb c e# so si s ck add. 012345678 add. add. 52 or d8 high impedance 15 16 23 24 31 mode 0 mode 3 1264 f09 .0 msb msb
14 advance information 512 kbit spi serial flash sst25vf512a ?2005 silicon storage technology, inc. s71264-01-000 1/05 chip-erase the chip-erase instruction clear s all bits in the device to ffh. a chip-erase instruction will be ignored if any of the memory area is protected. prior to any write operation, the write-enable (wren) instruction must be executed. ce# must remain active low for the duration of the chip-erase instruction sequence. the chip-erase instruction is initiated by executing an 8-bit command, 60h or c7h. ce# must be driven high before the instruction is executed. the user may poll the busy bit in the software status register or wait t ce for the completion of the internal self-timed chip-erase cycle. see figure 10 for the chip-erase sequence. figure 10: c hip -e rase s equence read-status-register (rdsr) the read-status-register (rdsr) instruction allows read- ing of the status register. the status register may be read at any time even during a write (program/erase) operation. when a write operation is in progress, the busy bit may be checked before sending any new commands to assure that the new commands are properly received by the device. ce# must be driven low before the rdsr instruction is entered and remain low until the status data is read. read- status-register is continu ous with ongoing clock cycles until it is terminated by a low to high transition of the ce#. see figure 11 for the rdsr instruction sequence. figure 11: r ead -s tatus -r egister (rdsr) s equence c e# so si s ck 01234567 60 or c7 high impedance mode 0 mode 3 1264 f10.0 msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1264 f11 .0 mode 3 s ck si so c e# bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 05 mode 0 high impedance status register out msb msb
advance information 512 kbit spi serial flash sst25vf512a 15 ?2005 silicon storage technology, inc. s71264-01-000 1/05 write-enable (wren) the write-enable (wren) instruction sets the write- enable-latch bit to 1 allowing write operations to occur. the wren instruction must be executed prior to any write (program/erase) operation. ce# must be driven high before the wren instruction is executed. figure 12: w rite e nable (wren) s equence write-disable (wrdi) the write-disable (wrdi) instruction resets the write- enable-latch bit and aai bit to 0 disabling any new write operations from occurring. ce# must be driven high before the wrdi instruction is executed. figure 13: w rite d isable (wrdi) s equence enable-write-status-register (ewsr) the enable-write-status-register (ewsr) instruction arms the write-status-register (wrsr) instruction and opens the status register for alteration. the enable-write- status-register instruction does not have any effect and will be wasted, if it is not followed immediately by the write- status-register (wrsr) instruction. ce# must be driven low before the ewsr instruction is entered and must be driven high before the ewsr instruction is executed. c e# so si s ck 01234567 06 high impedance mode 0 mode 3 1264 f12.0 msb c e# so si s ck 01234567 04 high impedance mode 0 mode 3 1264 f13. 0 msb
16 advance information 512 kbit spi serial flash sst25vf512a ?2005 silicon storage technology, inc. s71264-01-000 1/05 write-status-register (wrsr) the write-status-register instruction works in conjunction with the enable-write-status-register (ewsr) instruction to write new values to the bp1, bp0, and bpl bits of the status register. the write-status-register instruction must be executed immediately after the execution of the enable- write-status-register instruction (very next instruction bus cycle). this two-step instruction sequence of the ewsr instruction followed by the wrsr instruction works like sdp (software data protection) command structure which prevents any accidental alteration of the status register val- ues. the write-status-register instruction will be ignored when wp# is low and bpl bit is set to ?1?. when the wp# is low, the bpl bit can only be set from ?0? to ?1? to lock- down the status register, but cannot be reset from ?1? to ?0?. when wp# is high, the lock-down function of the bpl bit is disabled and the bpl, bp0, and bp1 bits in the status reg- ister can all be changed. as long as bpl bit is set to 0 or wp# pin is driven high (v ih ) prior to the low-to-high transi- tion of the ce# pin at the end of the wrsr instruction, the bp0, bp1, and bpl bit in the status register can all be altered by the wrsr instruction. in this case, a single wrsr instruction can set the bpl bit to ?1? to lock down the status register as well as altering the bp0 and bp1 bit at the same time. see table 3 for a summary description of wp# and bpl functions. ce# must be driven low before the command sequence of the wrsr instruction is entered and driven high before the wrsr instruction is executed. see figure 14 for ewsr and wrsr instruction sequences. figure 14: e nable -w rite -s tatus -r egister (ewsr) and w rite -s tatus -r egister (wrsr) s equence 1264 f14 .0 mode 3 high impedance mode 0 status register in 76543210 msb msb msb 01 mode 3 s ck si so c e# mode 0 50 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
advance information 512 kbit spi serial flash sst25vf512a 17 ?2005 silicon storage technology, inc. s71264-01-000 1/05 read-id the read-id instruction identifies the device as sst25vf512a and manufacturer as sst. the device information can be read from executing an 8-bit command, 90h or abh, followed by address bits [a 23 -a 0 ]. following the read-id instruction, the manufacturer?s id is located in address 00000h and the device id is located in address 00001h. once the device is in read-id mode, the manu- facturer?s and device id output data toggles between address 00000h and 00001h until terminated by a low to high transition on ce#. figure 15: r ead -id s equence 1264 f15.0 c e# so si s ck 00 012345678 00 add 1 90 or ab high impedance 15 16 23 24 31 32 39 40 47 48 55 56 63 bf device id bf device id note: the manufacturer's and device id output stream is continuous until terminated by a low to high transition on ce#. 1. 00h will output the manfacturer's id first and 01h will output device id first before toggling between the two. high impedanc e mode 3 mode 0 msb msb msb
18 advance information 512 kbit spi serial flash sst25vf512a ?2005 silicon storage technology, inc. s71264-01-000 1/05 electrical specifications absolute maximum stress ratings (applied conditions greater than t hose listed under ?absolute maximum stress ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these conditions or conditions greater t han those defined in the operational sections of this data sheet is not implied. exposu re to absolute maximum stress rating co nditions may affect device reliability.) temperature under bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55c to +125c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65c to +150c d. c. voltage on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0. 5v to v dd +0.5v transient voltage (<20 ns) on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0v to v dd +2.0v package power dissipation capability (t a = 25c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0w surface mount lead soldering temperature 1 (10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260c 1. compliant with jedec standard j-std-020b output short circuit current 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ma 2. output shorted for no more than one second. no more than one output shorted at a time. o perating r ange range ambient temp v dd commercial 0c to +70c 2.7-3.6v industrial -40c to +85c 2.7-3.6v extended -20c to +85c 2.7-3.6v ac c onditions of t est input rise/fall time . . . . . . . . . . . . . . . 5 ns output load . . . . . . . . . . . . . . . . . . . . . c l = 30 pf see figures 20 and 21 table 7: dc o perating c haracteristics v dd = 2.7-3.6v symbol parameter limits test conditions min max units i ddr read current 10 ma ce#=0.1 v dd /0.9 v dd @20 mhz, so=open i ddw program and erase current 30 ma ce#=v dd i sb standby current 15 a ce#=v dd , v in =v dd or v ss i li input leakage current 1 a v in =gnd to v dd , v dd =v dd max i lo output leakage current 1 a v out =gnd to v dd , v dd =v dd max v il input low voltage 0.8 v v dd =v dd min v ih input high voltage 0.7 v dd vv dd =v dd max v ol output low voltage 0.2 v i ol =100 a, v dd =v dd min v oh output high voltage v dd -0.2 v i oh =-100 a, v dd =v dd min t7.9 1264 table 8: r ecommended s ystem p ower - up t imings symbol parameter minimum units t pu-read 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. v dd min to read operation 10 s t pu-write 1 v dd min to write operation 10 s t8.0 1264
advance information 512 kbit spi serial flash sst25vf512a 19 ?2005 silicon storage technology, inc. s71264-01-000 1/05 table 9: c apacitance (t a = 25c, f=1 mhz, other pins open) parameter description test condition maximum c out 1 output pin capacitance v out = 0v 12 pf c in 1 input capacitance v in = 0v 6 pf t9.0 1264 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. table 10: r eliability c haracteristics symbol parameter minimum spec ification units test method n end 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. endurance 10,000 cycles jedec standard a117 t dr 1 data retention 100 years jedec standard a103 i lt h 1 latch up 100 + i dd ma jedec standard 78 t10.0 1264 table 11: ac o perating c haracteristics v dd = 2.7-3.6v limits 20 mhz 33 mhz symbol parameter min max min max units f clk serial clock frequency 20 33 mhz t sckh serial clock high time 20 13 ns t sckl serial clock low time 20 13 ns t sckr 1 1. maximum serial clock rise and fall times may be limited by t sckh and t sckl requirements. serial clock rise time (slew rate) 0.1 0.1 v/ns t sckf 1 serial clock fall time (slew rate) 0.1 0.1 v/ns t ces 2 2. relative to sck. ce# active setup time 20 12 ns t ceh 2 ce# active hold time 20 12 ns t chs 2 ce# not active setup time 10 10 ns t chh 2 ce# not active hold time 10 10 ns t cph ce# high time 100 100 ns t chz ce# high to high-z output 20 14 ns t clz sck low to low-z output 0 0 ns t ds data in setup time 5 3 ns t dh data in hold time 5 3 ns t hls hold# low setup time 10 10 ns t hhs hold# high setup time 10 10 ns t hlh hold# low hold time 15 10 ns t hhh hold# high hold time 10 10 ns t hz hold# low to high-z output 20 14 ns t lz hold# high to low-z output 20 14 ns t oh output hold from sck change 0 0 ns t v output valid from sck 20 12 ns t se sector-erase 25 25 ms t be block-erase 25 25 ms t sce chip-erase 100 100 ms t bp byte-program 20 20 s t11.0 1264
20 advance information 512 kbit spi serial flash sst25vf512a ?2005 silicon storage technology, inc. s71264-01-000 1/05 figure 16: s erial i nput t iming d iagram figure 17: s erial o utput t iming d iagram high-z high-z c e# so si s ck msb lsb t ds t dh t chh t ces t ceh t chs t sckr t sckf t cph 1264 f16.0 1264 f17.0 c e# si so s ck msb t clz t v t sckh t chz t oh t sckl lsb
advance information 512 kbit spi serial flash sst25vf512a 21 ?2005 silicon storage technology, inc. s71264-01-000 1/05 figure 18: h old t iming d iagram figure 19: p ower - up t iming d iagram t hz t lz t hhh t hls t hlh t hhs 1264 f18.0 h old# ce# sck so si time v dd min v dd max v dd device fully accessible t pu-read t pu-write chip selection is not allowed. all commands are rejected by the device. 1264 f19.0
22 advance information 512 kbit spi serial flash sst25vf512a ?2005 silicon storage technology, inc. s71264-01-000 1/05 figure 20: ac i nput /o utput r eference w aveforms figure 21: a t est l oad e xample 1264 f20.0 reference points output input v ht v lt v ht v lt v iht v ilt ac test inputs are driven at v iht (0.9v dd ) for a logic ?1? and v ilt (0.1v dd ) for a logic ?0?. measurement reference points for inputs and outputs are v ht (0.7v dd ) and v lt (0.3v dd ). input rise and fall times (10% ? 90%) are <5 ns. note: v ht - v high te s t v lt - v low te s t v iht - v input high test v ilt - v input low test 1264 f21.0 to tester t o dut c l
advance information 512 kbit spi serial flash sst25vf512a 23 ?2005 silicon storage technology, inc. s71264-01-000 1/05 product ordering information valid combinations for sst25vf512a sst25vf512a-33-4c-sa SST25VF512A-33-4C-QA sst25vf512a-33-4c-sae SST25VF512A-33-4C-QAe sst25vf512a-33-4i-sa sst25vf512a-33-4i-qa sst25vf512a-33-4i-sae sst25vf512a-33-4i-qae sst25vf512a-33-4e-sa sst25vf512a-33-4e-qa sst25vf512a-33-4e-sae sst25vf512a-33-4e-qae note: valid combinations are those products in mass producti on or will be in mass production. consult your sst sales representative to confirm availability of valid combinat ions and to determine availability of new combinations. environmental attribute e 1 = non-pb package modifier a = 8 leads or contacts package type s = soic q = wson temperature range c = commercial = 0c to +70c i = industrial = -40c to +85c e = extended = -20c to +85c minimum endurance 4 = 10,000 cycles operating frequency 33 = 33 mhz device density 512 = 512 kbit voltag e v = 2.7-3.6v product series 25 = serial peripheral interface flash memory 1. environmental suffix ?e? denotes non-pb solder. sst non-pb solder devices are ?rohs compliant?. device speed suffix1 suffix2 sst25 v fxxxa -xxx -x x -x x x
24 advance information 512 kbit spi serial flash sst25vf512a ?2005 silicon storage technology, inc. s71264-01-000 1/05 packaging diagrams 8- lead s mall o utline i ntegrated c ircuit (soic) 150 mil body width (4.9 mm x 6 mm ) sst p ackage c ode : sa 08-soic-5x6-sa-8 note: 1. complies with jedec publication 95 ms-012 aa dimensions, although some dimensions may be more stringent. 2. all linear dimensions are in millimeters (max/min). 3. coplanarity: 0.1 mm 4. maximum allowable mold flash is 0.15 mm at the package ends and 0.25 mm between leads. top view side view end view 5 .0 4 .8 6.20 5.80 4.00 3.80 pin #1 i dentifier 0.51 0.33 1.27 bsc 0.25 0.10 1.75 1.35 7? 4 places 0.25 0.19 1.27 0.40 45? 7? 4 places 0? 8? 1mm
advance information 512 kbit spi serial flash sst25vf512a 25 ?2005 silicon storage technology, inc. s71264-01-000 1/05 8- contact v ery - very - thin s mall o utline n o - lead (wson) sst p ackage c ode : qa table 12: r evision h istory number description date 00 initial release jun 2004 01 added rohs compliance information on page 1 and in the ?product ordering infor- mation? on page 23 updated the surface mount lead temperature from 240c to 260c and the time from 3 seconds to 10 seconds on page 18. jan 2005 note: 1. all linear dimensions are in millimeters (max/min). 8-wson-6x5-qa-8 4.00 0.10 1.27 bs c pin #1 0.48 0.35 0.076 3.40 0.10 0.25 0.19 5.00 0.10 6.00 0.10 0.05 max 0.70 0.50 0.80 0.70 0.80 0.70 pin #1 c orner top view bottom view cross section side view 1mm silicon storage technology, inc. 1171 sonora court sunnyvale, ca 94086 telephone 408-735-9110 fax 408-735-9036 www.superflash.com or www.sst.com

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